A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration

This paper presents a time-interleaved (TI) successive-approximation-register (SAR) ADC with a fast variance-based timing-skew calibration technique. It uses a single comparator-based window detector to calibrate the timing skew. It has low-hardware cost and 104 times faster convergence speed compared to prior variance-based timing skew calibration technique. The proposed technique brings collateral benefits of offset mismatch calibration. A prototype 10-b 800MS/s ADC in 40nm CMOS achieves Nyquist-rate SNDR of 48 dB and consumes 9.8mW, leading to a Walden FoM of 59-fJ/conversion-step.

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