Critical charge concepts for CMOS SRAMs

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge call be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must take into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.

[1]  P. T. McDonald,et al.  Practical approach to ion track energy distribution , 1988 .

[2]  Edward Petersen,et al.  Geometrical factors in SEE rate calculations , 1993 .

[3]  C. L. Axness,et al.  Mechanisms Leading to Single Event Upset , 1986, IEEE Transactions on Nuclear Science.

[4]  Barney Lee Doyle,et al.  Ion-beam-induced charge-collection imaging of CMOS ICs , 1993 .

[5]  H. T. Weaver.  Soft error stability of p-well versus n-well CMOS latches derived from 2-D transient simulations , 1988, Technical Digest., International Electron Devices Meeting.

[6]  A. B. Campbell,et al.  Alpha-, boron-, silicon- and iron-ion-induced current transients in low-capacitance silicon and GaAs diodes , 1988 .

[7]  R. Koga,et al.  Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMs , 1982, IEEE Transactions on Nuclear Science.

[8]  A. B. Campbell,et al.  Charge collection from focussed picosecond laser pulses , 1988 .

[9]  H.T. Weaver,et al.  RAM cell recovery mechanisms following high-energy ion strikes , 1987, IEEE Electron Device Letters.

[10]  D. G. Clemons,et al.  Fabrication and total dose testing of a 256 K*1 radiation-hardened SRAM , 1988 .

[11]  S. E. Diehl,et al.  Comparisons of Single Event Vulnerability of GaAs SRAMS , 1986, IEEE Transactions on Nuclear Science.

[12]  J. Choma,et al.  Single Event Upset in SOS Integrated Circuits , 1987, IEEE Transactions on Nuclear Science.

[13]  H.T. Weaver,et al.  Memory SEU simulations using 2-D transport calculations , 1985, IEEE Electron Device Letters.

[14]  Lloyd W. Massengill,et al.  Effects of process parameter distributions and ion strike locations on SEU cross-section data (CMOS SRAMs) , 1993 .

[15]  John Choma,et al.  Mixed-mode PISCES-SPICE coupled circuit and device solver , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  John R. Hauser,et al.  Simulation Approach for Modeling Single Event Upsets on Advanced CMOS SRAMS , 1985, IEEE Transactions on Nuclear Science.

[17]  R. L. Woodruff,et al.  Three-dimensional numerical simulation of single event upset of an SRAM cell , 1993 .

[18]  J. C. Pickel,et al.  Rate prediction for single event effects-a critique , 1992 .

[19]  W. A. Kolasinski,et al.  Cost-effective numerical simulation of SEU , 1988 .

[20]  R. Koga,et al.  SEU characterization of a hardened CMOS 64K and 256K SRAM , 1989 .

[21]  M. R. Pinto,et al.  The effects of ion track structure in simulating single event phenomena , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).

[22]  M. Alles,et al.  Model for CMOS/SOI single-event vulnerability , 1989 .

[23]  P. S. Winokur,et al.  Three-dimensional simulation of charge collection and multiple-bit upset in Si devices , 1994 .

[24]  R. R. O'Brien,et al.  A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices , 1981, IEEE Electron Device Letters.

[25]  H. T. Weaver,et al.  Comparison of 2D Memory SEU Transport Simulation with Experiments , 1985, IEEE Transactions on Nuclear Science.

[26]  R. Koga,et al.  Scaling studies of CMOS SRAM soft-error tolerances—From 16K to 256K , 1987, 1987 International Electron Devices Meeting.