Development of architecture and software technologies in high-performance low-power SoC design

For the success of an SoC design, a design platform and some key design technologies are needed. For this purpose, a research project in "Technology Development Program for Academia" was granted recently in Taiwan to develop the following technologies toward a high-performance low-power SoC design platform. First, a soft intellectual property (soft IP) and related RTOS, compiler, and integrated design environment (IDE) software of an Advanced Taiwan VLTW DSP Processor Core, which can be used as the Star IP of an SoC design platform, will be developed. Second, low-power and low-voltage digital and mixed-signal circuit design technologies will be developed based on the advanced MTCMOS process. Third, some key multimedia and communication soft or hard IPs will be developed. The developed advanced key technologies can be used as the technology driver to facilitate the design of SoC-based products, and they will also help to enhance the design capability of the Taiwan SoC industry. In this paper, we introduce the research project and focus on architecture and software technologies developing in one of the subitems.

[1]  B. E. Eckbo,et al.  Appendix , 1826, Epilepsy Research.

[2]  Grant Martin,et al.  A Design Chain for Embedded Systems , 2002, Computer.

[3]  Liang-Gee Chen,et al.  Perspectives of multimedia SoC , 2003, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682).

[4]  A. Maxim.  Notice of Violation of IEEE Publication PrinciplesA 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation , 2005, IEEE Journal of Solid-State Circuits.

[5]  P. Pirsch,et al.  An SoC with two multimedia DSPs and a RISC core for video compression applications , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[6]  K. Ishibashi,et al.  An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs , 2004, IEEE Journal of Solid-State Circuits.

[7]  J. Fossum,et al.  On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs , 2005, IEEE Transactions on Electron Devices.

[8]  Chong-Min Kyung,et al.  Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Jens Sparsø,et al.  Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.