An 8-channel fully differential analog front-end for neural recording

An 8-channel, analog front-end chip for neural recording is presented in this paper. The chip consists of eight neural recording amplifiers with tunable bandwidth and gain, eight 4th-order Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation (SAR) analog-to-digital converter (ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to several hundred Hz, and 3.77 μVrms referred noise. The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4. The chip is designed and fabricated in 0.18-μm CMOS process. We successfully performed simultaneous multi-channel recording in vitro experiment using the neural recording chip.

[1]  Kensall D. Wise,et al.  Band-tunable and multiplexed integrated circuits for simultaneous recording and stimulation with microelectrode arrays , 2005, IEEE Transactions on Biomedical Engineering.

[2]  Eugenio Culurciello,et al.  An 8-bit, 1mW successive approximation ADC in SOI CMOS , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[3]  R. Genov,et al.  256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes , 2009, IEEE Journal of Solid-State Circuits.

[4]  Reid R. Harrison,et al.  A low-power, low-noise CMOS amplifier for neural recording applications , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[5]  R.R. Harrison,et al.  Wireless Neural Recording With Single Low-Power Integrated Circuit , 2009, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[6]  David Sander,et al.  A low-power CMOS neural amplifier with amplitude measurements for spike sorting , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[7]  S. O'Driscoll,et al.  Neurons to Silicon: Implantable Prosthesis Processor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[8]  Mohamad Sawan,et al.  Wavelet transforms dedicated to compress recorded ENGs from multichannel implants: comparative architectural study , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[9]  R. R. Harrison,et al.  A low-power low-noise CMOS amplifier for neural recording applications , 2003, IEEE J. Solid State Circuits.

[10]  Xu Zhang,et al.  A low-noise fully-differential CMOS preamplifier for neural recording applications , 2011, Science China Information Sciences.

[11]  Moo Sung Chae,et al.  Design Optimization for Integrated Neural Recording Systems , 2008, IEEE Journal of Solid-State Circuits.

[12]  K. Najafi,et al.  A Wireless Implantable Microsystem for Multichannel Neural Recording , 2009, IEEE Transactions on Microwave Theory and Techniques.