Increasing EM Robustness of Placement and Routing Solutions based on Layout-Driven Discretization
暂无分享,去创建一个
[1] Thomas Weiland,et al. Self-consistent simulations of transient heating effects in electrical devices using the finite integration technique , 2001 .
[2] Jens Lienig,et al. Load-Aware Redundant Via Insertion for Electromigration Avoidance , 2016, ISPD.
[3] Nadine Gottschalk,et al. Vlsi Physical Design From Graph Partitioning To Timing Closure , 2016 .
[4] Edward J. Walsh,et al. DART system analysis. , 2005 .
[5] Matthew Hogan,et al. Electromigration analysis of full-chip integrated circuits with hydrostatic stress , 2014, 2014 IEEE International Reliability Physics Symposium.
[6] M. Welbourne. More on Moore , 1992 .
[7] Paul D. Franzon,et al. FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).
[8] Igor L. Markov,et al. VLSI Physical Design - From Graph Partitioning to Timing Closure , 2011 .
[9] Reiner Kirchheim,et al. Stress and electromigration in Al-lines of integrated circuits , 1992 .
[10] Farid N. Najm,et al. Theoretical predictions of EM-induced degradation in test-structures and on-chip power grids with analytical and numerical analysis , 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).
[11] M. Korhonen,et al. Stress evolution due to electromigration in confined metal lines , 1993 .