Evaluation of emerging TSV-enabled main memories on the PARSEC benchmark

This paper evaluates emerging TSV-interconnected memory technologies employed as the main memory of 3D Symmetric MultiProcessing (SMP). As the target architecture, we implemented a typical 3D SMP including L1 and L2 caches together with some tiers of main memory. Besides, we employed DDR3 as a baseline comparison to normalize all results. The experimental results show a tradeoff between energy efficiency and execution time when using six memory technologies executing a set of applications of PARSEC benchmark on Gem5. All evaluated memories reveal significant reductions in energy consumption with some penalization on the execution time. Additionally, HBM shows to be the most promising one, reducing more than five times the energy consumption and giving a small performance boost than DDR3, in general.

[1]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[2]  Luca Benini,et al.  A Logic-base Interconnect for Supporting Near Memory Computation in the Hybrid Memory Cube , 2014 .

[3]  Thomas F. Wenisch,et al.  Simulating DRAM controllers for future system architecture exploration , 2014, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[4]  Sally A. McKee,et al.  Hitting the memory wall: implications of the obvious , 1995, CARN.

[5]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[6]  U Uri Wiener.  Modeling and analysis of a cache coherent interconnect , 2012 .

[7]  Li Liu,et al.  Direct distributed memory access for CMPs , 2014, J. Parallel Distributed Comput..

[8]  Jan Reineke,et al.  Ascertaining Uncertainty for Efficient Exact Cache Analysis , 2017, CAV.

[9]  Hsien-Hsin S. Lee,et al.  An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[10]  Paul Rosenfeld,et al.  Performance Exploration of the Hybrid Memory Cube , 2014 .