Toward advanced parallel processing: exploiting parallelism at task and instruction levels

The status of two projects that entail the development of a reconfigurable parallel processor system with 128 Sparc microprocessors and a superscalar processor with four operations proceeding in parallel is discussed. The design principles, system configuration, processing element, network architecture, and memory architecture of the reconfigurable processors (called KRPP) are described. The operating system for KRPP is discussed. The architecture for the superscalar (called a dynamically hazard-resolved, statically code-scheduled, nonuniform superscalar) is presented.<<ETX>>

[1]  William J. Bolosky,et al.  Mach: A New Kernel Foundation for UNIX Development , 1986, USENIX Summer.

[2]  David L. Black.  Scheduling support for concurrency and parallelism in the Mach operating system , 1990, Computer.

[3]  E. S. Lee,et al.  Performance enhancement of SISD processors , 1979, ISCA '79.

[4]  Michael D. Smith,et al.  Boosting beyond static scheduling in a superscalar processor , 1990, ISCA '90.

[5]  Norman P. Jouppi,et al.  Available instruction-level parallelism for superscalar and superpipelined machines , 1989, ASPLOS 1989.

[6]  Akira Fukuda,et al.  The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures , 1989, ICS '89.

[7]  Norman P. Jouppi,et al.  The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance , 1989, IEEE Trans. Computers.

[8]  Akira Fukuda,et al.  The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture , 1989, IFIP Congress.

[9]  James E. Smith,et al.  Instruction Issue Logic in Pipelined Supercomputers , 1984, IEEE Trans. Computers.

[10]  Robert J. McMillen,et al.  A survey of interconnection methods for reconfigurable parallel processing systems* , 1899, 1979 International Workshop on Managing Requirements Knowledge (MARK).

[11]  N. Irie,et al.  SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture , 1989, ISCA '89.

[12]  James E. Smith,et al.  Dynamic instruction scheduling and the Astronautics ZS-1 , 1989, Computer.

[13]  Jake K. Aggarwal,et al.  Reconfiguration Strategies for Parallel Architectures , 1985, Computer.

[14]  J. E. Thornton,et al.  Parallel operation in the control data 6600 , 1964, AFIPS '64 (Fall, part II).

[15]  Michael J. Flynn,et al.  Very high-speed computing systems , 1966 .

[16]  R. M. Tomasulo,et al.  An efficient algorithm for exploiting multiple arithmetic units , 1995 .

[17]  Svetlana P. Kartashev,et al.  Adptable Architectures for Supersystems , 1980, Computer.

[18]  Alan Jay Smith,et al.  Branch Prediction Strategies and Branch Target Buffer Design , 1995, Computer.

[19]  Akira Fukuda,et al.  An overview of the Kyushu University reconfigurable parallel processor , 1988, CARN.

[20]  Kevin P. McAuliffe,et al.  RP3 Processor-Memory Element , 1985, ICPP.

[21]  Hiroshi Hagiwara,et al.  A Dynamically Microprogrammable Computer with Low-Level Parallelism , 1980, IEEE Transactions on Computers.

[22]  Shinji Tomita,et al.  A computer with low-level parallelism QA-2: its applications to 3-D graphics and Prolog/Lisp machines , 1986, ISCA 1986.

[23]  Samuel H. Fuller,et al.  Cm*: a modular, multi-microprocessor , 1977, AFIPS '77.

[24]  Anoop Gupta,et al.  Process control and scheduling issues for multiprogrammed shared-memory multiprocessors , 1989, SOSP '89.

[25]  Randall Rettberg,et al.  Contention is no obstacle to shared-memory multiprocessing , 1986, CACM.