Efficient Implementation of IQ_VOQ Based Input Blocks in the Design of Routing Node for Uniform & Bursty Traffic

The rise in complexity of SOC (System-on-Chip) architectures has brought into focus the need for better communication models for SOCs. The traditional bus based approach is reaching its limit with the emergence of high core count SOCs. The theory and practices of wired communication networks is being applied to tackle communication issues in complex SOCs. This is referred to as the Network on Chip (NOC) model. Routers are one of the most important elements of an on chip network. The underlying architecture of a router is based on a crossbar switch as it offers higher throughput and lower latency due to point-to-point architecture. Homogenous sizes of the input module in the router may not be efficient as some cores may be underutilized while some of them may be overloaded. A heterogeneous size of the input module is preferred for the predicted traffic but bursty in nature. We proposed, input module of size 64_packet array for the most busy node in the design while the most underutilized input module can also satisfy the need of the packet array of size 16. For moderate traffic, the input module with 32 packet array can be an efficient solution. The Islip based IQ_VOQ is the most practical combination, popular in the CISCO router [12000 series]. The input module proposed here is based on Virtual output queuing while Islip scheduling algorithm is based on unfolding and folding concept. First, the RTL implementation of input module for 3-proposed design has been carried out and later it realized using a standard-cell-based ASIC flow using 90 nm saed-typ technology library of Synopsis Educational Design Kit.