Low-power accumulator (correlator)
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As part of our research effort in the development of low-energy numerical computing systems, we have considered the accumulator (correlator) discussed by Chandrakasan and Brodersen (see Proc. IEEE, vol. 83, no. 4, p. 498-523, 1995). The operation to be performed is the accumulation (summation) of 1024 samples which have a range from -7 to +7 and are represented in the two's complement number system. In this paper we describe an implementation which results in a smaller area and energy than that of the previous implementation. We show expressions for the energy consumption and give an example of the reduction achieved for independent and uniformly distributed sample values and a particular standard cell library.
[1] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.