Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders

Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the implementation of the layered architecture is not always straightforward because of the memory access conflicts in the a-posteriori information memory. In this paper, we focus our attention on a particular type of conflict introduced by the existence of multiple diagonal matrices in the DVB-T2 parity check matrix structure. We illustrate how the reordering of the matrix reduces the number of conflicts, at the cost of limiting the level of parallelism. We then propose a parity extending process to solve the remaining conflicts. Fixed point simulation results show coherent performance without modifying the layered architecture.

[1]  Naresh R. Shanbhag,et al.  High-throughput LDPC decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Michael Horstein,et al.  Review of 'Low-Density Parity-Check Codes' (Gallager, R. G.; 1963) , 1964, IEEE Transactions on Information Theory.

[3]  J.R. Cavallaro,et al.  High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems , 2006, 2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software.

[4]  Luca Fanucci,et al.  A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes , 2007, 2007 IFIP International Conference on Very Large Scale Integration.

[5]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[6]  Vishwas Sundaramurthy,et al.  Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes , 2006, 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings.

[7]  Luca Fanucci,et al.  Layered Decoding of Non-Layered LDPC Codes , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[8]  Vincent Berg,et al.  Low cost LDPC decoder for DVB-S2 , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[9]  Jean-Luc Danger,et al.  Lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes , 2003 .

[10]  Rudy Lauwereins,et al.  Design, Automation, and Test in Europe , 2008 .

[11]  D.E. Hocevar,et al.  A reduced complexity decoder architecture via layered decoding of LDPC codes , 2004, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004..

[12]  Hideki Imai,et al.  Reduced complexity iterative decoding of low-density parity check codes based on belief propagation , 1999, IEEE Trans. Commun..

[13]  Marco Alexandre Cravo Gomes,et al.  Flexible Parallel Architecture for DVB-S2 LDPC Decoders , 2007, IEEE GLOBECOM 2007 - IEEE Global Telecommunications Conference.

[14]  Frank Kienle,et al.  A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding , 2006, 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications.

[15]  Frank Kienle,et al.  A synthesizable IP core for DVB-S2 LDPC code decoding , 2005, Design, Automation and Test in Europe.

[16]  Naresh R. Shanbhag,et al.  Low-power VLSI decoder architectures for LDPC codes , 2002, ISLPED '02.

[17]  Dariush Divsalar,et al.  Construction of Protograph LDPC Codes with Linear Minimum Distance , 2006, 2006 IEEE International Symposium on Information Theory.