Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip
暂无分享,去创建一个
[1] Zhiyi Yu,et al. A 167-Processor Computational Platform in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.
[2] Luca Benini,et al. Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.
[3] Natalie D. Enright Jerger,et al. Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Fabrizio Petrini,et al. Cell Multiprocessor Communication Network: Built for Speed , 2006, IEEE Micro.
[5] Axel Jantsch,et al. TDM Virtual-Circuit Configuration for Network-on-Chip , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[6] Jiang Xu,et al. Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs , 2009, IEEE Micro.
[7] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[8] Fabien Clermidy,et al. A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip , 2008, IEEE Journal of Solid-State Circuits.
[9] S. Borkar,et al. An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.
[10] Chulwoo Kim,et al. A Compact and High Performance Switch for Circuit-Switched Network-On-Chip , 2006, 2006 IEEE International SOC Conference.
[11] A. Alvandpour,et al. A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications , 2007, 2007 IEEE Symposium on VLSI Circuits.
[12] Gerard J. M. Smit,et al. An energy-efficient reconfigurable circuit-switched network-on-chip , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.
[13] Eisse Mensink,et al. Low-Power, High-Speed Transceivers for Network-on-Chip Communication , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[14] Dake Liu,et al. SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.
[15] Natalie D. Enright Jerger,et al. Circuit-Switched Coherence , 2007, IEEE Computer Architecture Letters.
[16] Sudhakar Yalamanchili,et al. Interconnection Networks: An Engineering Approach , 2002 .
[17] Chulwoo Kim,et al. Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip , 2008, 2008 Second International Conference on Communications and Electronics.
[18] Kees Goossens,et al. AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.
[19] Yuhen Hu,et al. Wave-pipelined on-chip global interconnect , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[20] Sudhakar Yalamanchili,et al. A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks , 1995, IEEE Trans. Parallel Distributed Syst..
[21] Hoi-Jun Yoo,et al. Packet-switched on-chip interconnection network for system-on-chip applications , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.