An accurate and efficient probabilistic congestion estimation model in x architecture

Recently, the X architecture has been introduced to improve performance of the chip. Though the X architecture can reduce the wirelength significantly, routability remains a major concern in the design flow. In this paper, we formulate the congestion estimation in the X architecture based on the liquid routing technique. Based on the probabilistic analysis of the routing demand, a congestion estimation model in the X architecture is presented. An existing dynamic resource assignment (Dra) method is adopted in our model in order to obtain accurate congestion estimation. Experiments show that the congestion estimated by our model correlates well with post-routing congestion in the X architecture based on the liquid routing technique. The good accuracy and high efficiency of our model is also presented.

[1]  Steven L. Teig,et al.  The X architecture: not your father's diagonal wiring , 2002, SLIP '02.

[2]  Yici Cai,et al.  Dynamic global buffer planning optimization based on detail block locating and congestion analysis , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[3]  Shankar Krishnamoorthy,et al.  Estimating routing congestion using probabilistic analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Andrew B. Kahng,et al.  Accurate pseudo-constructive wirelength and congestion estimation , 2003, SLIP '03.

[5]  Majid Sarrafzadeh,et al.  On the behavior of congestion minimization during placement , 1999, ISPD '99.

[6]  Tsai-Ming Hsieh,et al.  A new effective congestion model in floorplan design , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  Morteza Saheb Zamani,et al.  Prediction and reduction of routing congestion , 2006, ISPD '06.

[8]  Majid Sarrafzadeh,et al.  Modeling and minimization of routing congestion , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[9]  Patrick Groeneveld,et al.  Is probabilistic congestion estimation worthwhile? , 2005, SLIP '05.

[10]  Yao-Wen Chang,et al.  Multilevel full-chip routing for the X-based architecture , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[11]  Yu Hu,et al.  A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design , 2005, SAMOS.

[12]  Yu Hu,et al.  DraXRouter: global routing in X-architecture with dynamic resource assignment , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[13]  Patrick Groeneveld,et al.  Probabilistic congestion prediction , 2004, ISPD '04.

[14]  Martin Zachariasen,et al.  A new paradigm for general architecture routing , 2004, GLSVLSI '04.

[15]  Evangeline F. Y. Young,et al.  Routability-driven floorplanner with buffer block planning , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Xianlong Hong,et al.  FREe: A Fast Routability Estimator , 2006, 2006 International Conference on Communications, Circuits and Systems.

[17]  Raia Hadsell,et al.  Improved global routing through congestion estimation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[18]  Chih-Liang Eric Cheng.  RISA: accurate and efficient placement routability modeling , 1994, ICCAD.