An 8-bit 300MS/s Switched-Current Pipeline ADC in 0.18µm CMOS

In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18um CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply.

[1]  Takashi Nara,et al.  A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter , 1998 .

[2]  A.H.M. van Roermund,et al.  A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption , 2005, IEEE Journal of Solid-State Circuits.

[3]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[4]  Patricia Desgreys,et al.  SC and SI techniques performances faced with technological advances [in CMOS] , 2002, 9th International Conference on Electronics, Circuits and Systems.

[5]  Shin-Il Lim,et al.  An 8-bit 1 Gsps CMOS pipeline ADC , 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

[6]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[7]  Andreas Kaiser,et al.  Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping , 2001, IEEE J. Solid State Circuits.

[8]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[9]  Deog-Kyoon Jeong,et al.  A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  John B. Hughes,et al.  Switched-capacitors versus switched-currents: a theoretical comparison [in CMOS] , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).