Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications

System reconfiguration of hardware resources has been done in multiple system domains. Such systems are usually found in the context of FPGAs, where reconfiguration is done usually over its primitives (e.g., LUTs, Flip-Flops). Or even in the context of MPSoC designs, where core management (e.g., lock-step operation in multi-core designs) is the most used approach. However, recent works have shown that configuration at Functional Units (FUs) granularity might come with benefits. For example, it can increase the configuration space due to its finer granularity, and, as a consequence, the options to deal with problems (e.g., due to aging) in the units itself. Within this context, this paper presents a system capable to configure its FUs (e.g., ALUs, multipliers, dividers) into different operation modes. The system uses an Operating System to control HW reconfiguration during process switching time and takes into account the health state of its units in a mixed-criticality applications scenario. Results show that, within this scenario, the system is able to reconfigure itself accomplishing health state modifications of its HW elements.

[1]  Christian Siemers,et al.  Self-aware and self-expressive driven fault tolerance for embedded systems , 2014, 2014 IEEE Symposium on Intelligent Embedded Systems (IES).

[2]  Chrysostomos Nicopoulos,et al.  DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors , 2016, IEEE Transactions on Computers.

[3]  Sergei Devadze,et al.  Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure , 2017, IEEE Design & Test.

[4]  Norbert Wehn,et al.  Reliable on-chip systems in the nano-era: Lessons learnt and future trends , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  Michael Hübner,et al.  Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications , 2017, ArXiv.

[6]  Felix Mühlbauer,et al.  A fault tolerant dynamically scheduled processor with partial permanent fault handling , 2018, 2018 IEEE 19th Latin-American Test Symposium (LATS).

[7]  Abdulazim Amouri,et al.  Altering LUT configuration for wear-out mitigation of FPGA-mapped designs , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[8]  Hyejeong Hong,et al.  Lifetime Reliability Enhancement of Microprocessors , 2015, ACM Comput. Surv..

[9]  Emre Ozer,et al.  Work-in-progress: a “high resilience” mode to minimize so error vulnerabilities in ARM cortex-R CPU pipelines , 2017, 2017 International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES).

[10]  Michael Hübner,et al.  A Dynamic Partial Reconfigurable Overlay Framework for Python , 2018, ARC.

[11]  Nikil D. Dutt,et al.  Design methodologies for enabling self-awareness in autonomous systems , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Cristiana Bolchini,et al.  A dynamic reliability management framework for heterogeneous multicore systems , 2017, 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[13]  Jörg Nolte,et al.  Low latency reconfiguration mechanism for fine-grained processor internal functional units , 2019, 2019 IEEE Latin American Test Symposium (LATS).