Real-time fault-tolerance with hot-standby topology for conditional sum adder

Abstract This paper presents the design philosophy of a fault tolerant conditional sum adder that uses hot-standby technique, which is an online swapping process of faulty components of a circuit by fault-free spares without interrupting the normal operation of the system. We have used dynamic recovery scheme in fault detection and correction and made the method efficient in terms of area and test complexity compared to the existing approaches. The adder here is sliced into smaller sub-modules for ease of testing and one hot spare is used for reconfiguration purpose. Number of test vectors in the proposed technology is independent of the word-length and due to cascadable nature of the design, we can increase the word-length while tolerating multiple faults.

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