Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips

A memory architecture with the capability of self-testing and self-repairing is presented. The contributions of this memory architecture are twofold. First, because it incorporates self-testing and self-repairing structures, the memory chip can perform tests, locate faults, and repair itself without any external assistance from either test engineers or test equipment. This will greatly improve the functional yield and reduce the production cost. Second, the hierarchical organization used to achieve optimal conditions for memory access time also helps increase the efficiency of the self-testing and self-repairing structures. >

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