A novel design methodology to optimize the speed and power of the CNTFET circuits

Carbon nanotubes with their superior properties have proved to be a potential alternative device to CMOS. In this paper, circuit optimization methods for high performance and low power CNFEFT circuit are proposed. The proposed design methods for CNTFET circuit address how to decide the optimum CNTFET parameters such as pitch, diameter, number of CNTs (Carbon Nano Tube), optimum fan-out factor and logical efforts to deliver the minimum power-delay product. The proposed method makes it possible to accomplish 56% dynamic power reduction and 22% less delay by optimizing the pitch, number of CNTs, fan-out factor, and logical efforts compared to the circuits that are not optimized and screening effects are ignored.

[1]  Richard Martel,et al.  Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes , 2002 .

[2]  Kjell O. Jeppson,et al.  CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Carbon nanotube electronics , 2002 .

[4]  H. Wong,et al.  A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors , 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

[5]  S. Datta,et al.  Performance projections for ballistic carbon nanotube field-effect transistors , 2002 .

[6]  H. Wong,et al.  Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels , 2007, IEEE Transactions on Electron Devices.

[7]  Jing Guo,et al.  Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-κ Gate Dielectrics , 2004 .

[8]  H. Wong,et al.  Carbon nanotube field effect transistors for logic applications , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[9]  J. Meindl,et al.  Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) , 2005, IEEE Electron Device Letters.

[10]  S. Wind,et al.  Carbon nanotube electronics , 2003, Digest. International Electron Devices Meeting,.