Power Saving Effect of Dynamic Partial Reconfiguration on FPGA

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Array (FPGA) is able to update circuits equal to software without halting an entire system and achieve power saving by emptying unused circuits on the device. But, the way designing and managing circuit data of the DPR are dependent on each designer. Thus, the DPR has not become widespread because it's difficult to share the intellectual properties and execution models over different engineers. This paper defines the initial framework of the design and management methods for the DPR that the FPGA performs by itself, self DPR. We perform the case study based on the proposed framework. In addition, we indicates the effect of power saving depending on the circuit blanking using prototype.