Release method, system and logic module for buffered address

The invention provides a method for releasing a cache address, which includes the steps as follows: when a message is transmitted to a CPU from a logic module, the CPU inquires about the packet information from the logic module, then in light of the packet information, the CPU reads the message from the logic module; after reading the message, the CPU reads the packet information corresponding tothe message from the logic module which then releases the cache address contained in the packet information. The invention also provides a logic module and a cache address releasing system. The invention can ensure that the cache address is released appropriately, thus preventing the occurrence of releasing the cache address in a wrong way.