Bipartitioning circuits using TABU search

VLSI circuit partitioning is an extensively studied problem. Various iterative improvement based heuristics have been, proposed for obtaining reasonably good solutions. In this paper we explore the applicability of TABU search for partitioning of electrical circuits. We briefly describe the TABU search and its application to circuit or graph partitioning. We have generated experimental results on a variety of standard benchmark circuits. Our results match in quality, and at times improve, the tightest known results in the partitioning literature. We have shown extensive comparison with at least six very well known methods for circuit partitioning.

[1]  Andrew B. Kahng,et al.  Multilevel circuit partitioning , 1997, DAC.

[2]  Andrew B. Kahng,et al.  A hybrid multilevel/genetic approach for circuit partitioning , 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

[3]  Frank M. Johannes Partitioning of VLSI circuits and systems , 1996, DAC '96.

[4]  N. Metropolis,et al.  Equation of State Calculations by Fast Computing Machines , 1953, Resonance.

[5]  Shantanu Dutt,et al.  VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, ICCAD 1996.

[6]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[7]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[8]  Konrad Doll,et al.  Partitioning Very Large Circuits Using Analytical Placement Techniques , 1994, 31st Design Automation Conference.

[9]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[10]  Charles J. Alpert,et al.  Spectral Partitioning: The More Eigenvectors, The Better , 1995, 32nd Design Automation Conference.

[11]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[12]  Andrew B. Kahng,et al.  New spectral methods for ratio cut partitioning and clustering , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Shantanu Dutt,et al.  VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, Proceedings of International Conference on Computer Aided Design.

[14]  S. Dutt New faster Kernighan-Lin-type graph-partitioning algorithms , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[15]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.