As 2nd and 3rd generation Focal Plane Arrays (FPA) become more complex, the readout integrated circuit (ROIC) has emerged as a major discriminator in system performance. The focus of development and advancement has traditionally involved the detector technology. Early ROICs were simple multiplexers that performed little if any signal processing on the detector diode signal. Advances in silicon fabrication processes for analog integrated circuits have opened a new era in IRFPAs where signal digital functions can be achieved on the focal plane. We present an overview of significant advances in the area of mixed mode ROIC designs that enable greater functionality and performance of the sensor chip assembly. Innovations, continuing progress in CMOS technology, and greater foundry access have allowed enhancements in practically every aspect of the ROIC, from sophisticated unit cells to lower noise and lower power signal paths to highly programmable digital support circuitry. Denser detector input circuits with active amplifiers (FEDI or CTIA) have been implemented in unit cells as small as 27 micrometer X 27 micrometer. In addition, multiple gain, temporal filtering, or spatial filtering capabilities have been incorporated into these small unit cells. Significant reductions in focal plane power have been fabricated and demonstrated enabling a factor of 2 increase in frame rates for very large staring FPAs and a factor of 4 increase in line rates for scanning FPAs. Other developments include, but are not limited to, alternative schemes for time-delayed integration (TDI) and breakthroughs for uncooled applications. As the chip designs increase in capability, greater systems on a chip are feasible, especially with more programmable features provided by the on-chip digital circuitry.