Code generation algorithms for digital signal processors

The dramatic reduction in the cost of electronic devices combined with large improvements in design productivity due to the use of automatic tools are gradually opening up the possibility for high-performance, very low cost computation. This is reflected in the increasing demand for high-performance portable devices which have low power consumption and cost. The best way to design such systems is to use dedicated architectures. Digital Signal Processors (DSPs) are specialized architectures which can provide these features for applications which require intensive numeric computation, like those running in telecommunication systems. This thesis deals with code generation for DSPs. It addresses two main problems in this area. The first is the generation of code for program basic blocks. The second is the problem of code generation for address computation. This work makes two contributions for the basic block code generation problem. First, it proposes a model for the processor architecture which captures the impact of the datapath design in the code generation algorithm. Based on this model, it proves the existence of an optimal O(n) algorithm for expression tree code generation for a class of DSP architectures. Experimental results are used to confirm the correctness of the algorithm. The contribution of this thesis for the address generation problem is an algorithm for the allocation of array references to address registers, which maximizes the use of the registers and reduces the cost of addressing operations in the program. Experiments are performed which show that the proposed optimization can considerably improve the final addressing code, when compared with code from the best optimizing compiler available for the target DSP.