Real-time high-energy physics applications on DECPeRLe-1 programmable active memory

The future Large Hadron Collider (LHC) to be built at CERN1 by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST2 (RD-11) group and DEC-PRL PAM3 team. We present implementations of the four foremost LHC algorithms on DECPeRLe-1 [1]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based machine built for just one of the algorithms [2]. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.

[1]  Laurent Moll,et al.  Programmable active memories in real-time tasks: implementing data-driven triggers for LHC experiments , 1995 .

[2]  Jean Vuillemin.  Fast linear Hough transform , 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).

[3]  E VuilleminJean,et al.  Programmable active memories , 1996 .

[4]  L. Moll,et al.  A Neural Network for Global Second Level Trigger - A Real-time Implementation on DecPeRLe-1 , 1995 .

[5]  Reinhard Männer,et al.  Enable-a systolic 2nd level trigger processor for track finding and e//spl pi/ discrimination for ATLAS/LHC , 1994 .

[6]  L. J. Levinson,et al.  A commercial image processing system considered for triggering in future LHC experiments , 1995 .

[7]  Laurent Moll,et al.  A PROGRAMMABLE ACTIVE MEMORY IMPLEMENTATION OF A NEURAL NETWORK FOR SECOND LEVEL TRIGGERING IN ATLAS , 1995 .

[8]  Beat Heeb,et al.  Chameleon: A Workstation of a Different Colour , 1992, FPL.

[9]  Jean Vuillemin.  On Computing Power , 1994, Programming Languages and System Architectures.

[10]  Mark Shand,et al.  Programmable active memories: reconfigurable systems come of age , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Jean Vuillemin,et al.  Introduction to programmable active memories , 1990 .

[12]  Arie Taal,et al.  Evaluating parallel architectures for two real-time applications with 100 kHz repetition rate (hadron collider data) , 1993 .

[13]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[14]  Reinhard Männer,et al.  Enable++: a second generation FPGA processor , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[15]  Mark Schlack,et al.  Digital Equipment Corp. , 1993 .

[16]  P. Bertin.  Memoires actives programmables : conception, realisation et programmation , 1993 .