On applying set covering models to test set compaction

Test set compaction is fundamental problem in digital system testing. In recent years, many competitive solutions have been proposed, most of which based on heuristics approaches. This paper studies the application of set covering models to the compaction of test sets, which can be used with any heuristic test set compaction procedure. For this purpose, recent and highly effective set covering algorithms are used. Experimental evidence suggests that the size of computed test sets can often be reduced by using set covering models and algorithms. Moreover a noteworthy empirical conclusion is that it may be preferable not to use fault simulation when the final objective is test set compaction.

[1]  Dorit S. Hochbaum,et al.  An optimal test compression procedure for combinational circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Sheldon B. Akers,et al.  On the Complexity of Estimating the Size of a Test Set , 1984, IEEE Transactions on Computers.

[3]  Sarita Thakar,et al.  On the generation of test patterns for combinational circuits , 1993 .

[4]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[5]  Yusuke Matsunaga.  MINT-An Exact Algorithm for Finding Minimum Test Set (Special Section on VLSI Design and CAD Algorithms) , 1993 .

[6]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[7]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[8]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  J.H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[10]  J. M. Silva.  Integer programming models for optimization problems in test generation , 1998 .

[11]  Joao Marques-Silva.  Integer Programming Models for Optimization Problems in Test Generation , 1998, ASP-DAC.

[12]  Michael H. Schulz,et al.  Improved deterministic test pattern generation with applications to redundancy identification , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Olivier Coudert,et al.  On solving covering problems , 1996, DAC '96.

[14]  Irith Pomeranz,et al.  The minimum test set problem for circuits with nonreconvergent fanout , 1991, J. Electron. Test..

[15]  Gert-Jan Tromp,et al.  Minimal Test Sets for Combinational Circuits , 1991, 1991, Proceedings. International Test Conference.