PSTA-based branch and bound approach to the silicon speedpath isolation problem

The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The identification of speed-limiting paths, or simply speedpaths, in silicon debug is a crucial step, required for both "fixing" failing paths and for accurate learning from silicon data. We propose using characterized, pre-silicon, variational timing models to identify speedpaths that can best explain the observed delays from silicon measurements. Delays of all logic paths are written as affine functions of process parameters, called hyperplanes, and a branch and bound approach is then applied to find the "best" path combinations. Our method has been tested on a set of ISCAS-89 circuits and the results show that it accurately identifies the speedpaths in most cases, and that this is achieved in a very efficient manner.

[1]  Li-C. Wang,et al.  On silicon-based speed path identification , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[2]  Sachin S. Sapatnekar,et al.  A framework for block-based timing sensitivity analysis , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[3]  Li-C. Wang,et al.  Speedpath prediction based on learning from a small set of examples , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[4]  Chandramouli V. Kashyap,et al.  Silicon Speedpath Measurement and Feedback into EDA flows , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[5]  Mario Paniccia,et al.  Novel optical probing technique for flip chip packaged microprocessors , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  Farid N. Najm,et al.  A Linear-Time Approach for Static Timing Analysis Covering All Process Corners , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[7]  Farinaz Koushanfar,et al.  Post-silicon timing characterization by compressed sensing , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Doug Josephson,et al.  The crazy mixed up world of silicon debug [IC validation] , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[9]  Farid N. Najm,et al.  Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.