Efficient Message Passing Architecture for High Throughput LDPC Decoder

In this paper, we propose an efficient message passing architecture for permutation matrices based LDPC code decoders. Min-sum algorithm is reformulated to facilitate significant reduction of routing complexity and memory usage. For a (2048, 1723) (6, 32) LDPC code with 4-bit quantization, 54% outgoing wires per variable node unit and 90% outgoing wires per check node unit can be saved. To further reduce hardware complexity, an optimized nonuniform quantization scheme using only 3 bits to represent each message has been investigated. The simulation result shows that it has only 0.25dB performance loss from the floating-point SPA

[1]  Jinghu Chen,et al.  Decoding low-density parity check codes with normalized APP-based algorithm , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[2]  In-Cheol Park,et al.  Loosely coupled memory-based decoding architecture for low density parity check codes , 2006, IEEE Trans. Circuits Syst. I Regul. Pap..

[3]  Keshab K. Parhi,et al.  VLSI implementation issues of TURBO decoder design for wireless applications , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[4]  Zhongfeng Wang,et al.  A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[5]  Ajay Dholakia,et al.  Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.

[6]  Shu Lin,et al.  A class of low-density parity-check codes constructed based on Reed-Solomon codes with two information symbols , 2003, IEEE Communications Letters.

[7]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[8]  A. J. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[9]  A. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[10]  Tong Zhang,et al.  On finite precision implementation of low density parity check codes decoder , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[11]  J. Huisken,et al.  A scalable architecture for LDPC decoding , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[12]  Zhongfeng Wang,et al.  A Memory Efficient Partially Parallel Decoder Architecture for QC-LDPC Codes , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..

[13]  D.J.C. MacKay,et al.  Good error-correcting codes based on very sparse matrices , 1997, Proceedings of IEEE International Symposium on Information Theory.

[14]  Frank R. Kschischang,et al.  Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[15]  Joseph R. Cavallaro,et al.  Semi-parallel reconfigurable architectures for real-time LDPC decoding , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[16]  Jeremy Thorpe,et al.  Memory-efficient decoding of LDPC codes , 2005, Proceedings. International Symposium on Information Theory, 2005. ISIT 2005..