Multiple catastrophic fault diagnosis of analog circuits considering the component tolerances

This paper deals with the diagnosis of multiple catastrophic faults, being cuts (open-circuits) of some connecting paths and/or short-circuits of some pairs of points in analog circuits. A method enabling us to detect and identify the faults, taking into account the deviations of the circuit parameters within their tolerance ranges, is developed. The method exploits an appropriate fault dictionary. The fault dictionary is used only for preliminary identification of the faults, because it is based on the analysis of the circuits with nominal parameters. The crucial point of the method is a verification procedure, proposed in this paper, based on the linear programming approach. It leads to the results considering the component variations within their tolerance ranges. In addition, a procedure for selecting appropriate test points, employing some evolutionary techniques, is developed. Although the approach presented in this paper is described in detail for linear circuits, it can be directly generalized to nonlinear circuits. Three numerical examples, including two linear and one nonlinear circuits, illustrate the proposed method and show its efficiency. Copyright © 2011 John Wiley & Sons, Ltd.

[1]  Michał Tadeusiewicz,et al.  An algorithm for multiple fault diagnosis in analogue circuits: Research Articles , 2006 .

[2]  Mohamed Fathy Abu El-Yazeed,et al.  A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification , 1999, J. Electron. Test..

[3]  Ada Fort,et al.  Automated selection of test frequencies for fault diagnosis in analog electronic circuits , 2005, IEEE Transactions on Instrumentation and Measurement.

[4]  M. Soma,et al.  Automatic analog test signal generation using multifrequency analysis , 1999 .

[5]  Shulin Tian,et al.  Selection of Global Minimal Test Points Set for Integer-Coded Fault Wise Table , 2009, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis.

[6]  Ozawa Analog methods for computer-aided circuit analysis & diagnosis , 1988 .

[7]  Gerardus Sierksma,et al.  Linear and integer programming - theory and practice , 1999, Pure and applied mathematics.

[8]  Michal Tadeusiewicz,et al.  Multiple catastrophic fault diagnosis of linear circuits considering the component tolerances , 2009, 2009 European Conference on Circuit Theory and Design.

[9]  M. Tadeusiewicz,et al.  An algorithm for soft-fault diagnosis of linear and nonlinear circuits , 2002 .

[10]  Farzan Aminian,et al.  Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor , 2001, J. Electron. Test..

[11]  José Luis Huertas,et al.  Analog and mixed-signal benchmark circuits-first release , 1997, Proceedings International Test Conference 1997.

[12]  Stanisław Hałgas,et al.  A method for fast simulation of multiple catastrophic faults in analogue circuits , 2010 .

[13]  Alston S. Householder,et al.  The Theory of Matrices in Numerical Analysis , 1964 .

[14]  Stefano Manetti,et al.  A Method for the Automatic Selection of Test Frequencies in Analog Fault Diagnosis , 2007, IEEE Transactions on Instrumentation and Measurement.

[15]  H. Schreiber Fault dictionary based upon stimulus design , 1979 .

[16]  Marcantonio Catelani,et al.  On the application of neural networks to fault diagnosis of electronic analog circuits , 1996 .

[17]  Feng Li,et al.  The invariance of node-voltage sensitivity sequence and its application in a unified fault detection dictionary method , 1999 .

[18]  Alok Barua,et al.  Fault diagnosis of analog integrated circuits , 2005 .

[19]  M. A. El-Gamal,et al.  Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits , 2007, J. Electron. Test..

[20]  Artur Wymyslowski,et al.  Simulated annealing as a global optimization algorithm used in numerical prototyping of electronic packaging , 2009, EuroSimE 2009 - 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems.

[21]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[22]  Dong Liu,et al.  Entropy-based optimum test points selection for analog fault dictionary techniques , 2004, IEEE Transactions on Instrumentation and Measurement.

[23]  Michal Tadeusiewicz,et al.  An algorithm for multiple fault diagnosis in analogue circuits , 2006, Int. J. Circuit Theory Appl..

[24]  Michał Tadeusiewicz,et al.  A method for fault diagnosis in linear electronic circuits , 2000, Int. J. Circuit Theory Appl..

[25]  V. C. Prasad,et al.  Fast algorithms for selection of test nodes of an analog circuit using a generalized fault dictionary approach , 1995 .

[26]  W. Hochwald,et al.  A dc approach for analog fault dictionary determination , 1979 .

[27]  Alkis A. Hatzopoulos,et al.  Improved analogue fault coverage estimation using probabilistic analysis , 2010 .

[28]  Yukiya Miura,et al.  Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[29]  V. C. Prasad,et al.  Selection of test nodes for analog fault diagnosis in dictionary approach , 2000, IEEE Trans. Instrum. Meas..

[30]  Michal Tadeusiewicz,et al.  An efficient method for simulation of multiple catastrophic faults , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[31]  J.W. Bandler,et al.  Fault diagnosis of analog circuits , 1985, Proceedings of the IEEE.

[32]  Jerzy Rutkowski,et al.  Genetic-Algorithm-Based Method for Optimal Analog Test Points Selection , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[33]  Dong Liu,et al.  A generalized fault diagnosis method in dynamic analogue circuits , 2002, Int. J. Circuit Theory Appl..