Reduced Interprocessor-Communication Architecture and its Implementation on EM-4

Abstract One of the most significant issues in building general purpose massively parallel computers is the integration of computation and communication in an efficient and cost-effective manner. This paper presents a way of integrating computation and communication from the viewpoint of the processor architecture. Two statements will be presented and examined: (1) computation and communication should be tightly coupled and their operation should be highly overlapped; and (2) communication structure should be efficient and simple, i.e. turnaround from data input to execution should be as short as possible using a simplified message handling mechanism. Briefly we can say ‘Fuse communication and computation, then reduce the fused structure as simple and efficient as possible’. The fused structure is called RICA, Reduced Interprocessor-Communication Architecture, in this paper. The word ‘Reduced’ here means the simplified structure of message handling, invocation of a new thread, computation and message generation. Based on the RICA design principles, the authors have developed the EM-series parallel computers, EM-4, EM-X and EM-5. This paper concentrates on the architecture and implementation of EM-4, whose first prototype has been fully operational since April 1990. The communication performance of EM-4 is comparable with its computation performance. These two primitives are efficiently and simply fused within the EM-4 architecture, i.e. a simple fused pipeline which performs message handling, instruction execution and packet output: message-handling time is two RISC clocks which is independent of executing processor instructions. This pipeline naturally includes a sequential RISC pipeline for executing local operations. Secondly this paper evaluates RICA by implementing on EM-4 several programming models generally considered ‘effective’ or ‘promising’. The multi-threaded model, message passing model and data-parallel model have been implemented and a shared-memory model is being implemented on EM-4. Performance of communication primitives for each model is measured on EM-4 prototype and reported here.