Optimum Circuits for Bit Reversal

This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2k , radix-4, and radix-8.

[1]  Peter Nilsson,et al.  Flexible baseband transmitter for OFDM , 2003 .

[2]  Donald Fraser,et al.  Array Permutation by Index-Digit Permutation , 1976, JACM.

[3]  Tuomas Järvinen.  Systematic Methods for Designing Stride Permutation Interconnections , 2004 .

[4]  J. Prado.  A new fast bit-reversal permutation algorithm based on a symmetry , 2004, IEEE Signal Processing Letters.

[5]  Keshab K. Parhi,et al.  A Pipelined FFT Architecture for Real-Valued Signals , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  F. Leighton,et al.  Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes , 1991 .

[7]  Alan Edelman,et al.  Index Transformation Algorithms in a Linear Algebra Framework , 1994, IEEE Trans. Parallel Distributed Syst..

[8]  S. Chakrabarti,et al.  On output reorder buffer design of bit reversed pipelined continuous data FFT architecture , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[9]  Maurice Bellanger,et al.  Digital processing of signals , 1989 .

[10]  Yun-Nan Chang,et al.  An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Juan Manuel Rius,et al.  New FFT bit-reversal algorithm , 1995, IEEE Trans. Signal Process..

[12]  Chao-Ming Chen,et al.  An Energy-Efficient Partial FFT Processor for the OFDMA Communication System , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  Mario Garrido Gálvez.  Efficient hardware architectures for the computation of the FFT and other related signal processing algorithms in real time , 2009 .

[14]  Daniel Massicotte,et al.  A novel approach for FFT data reordering , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[15]  T. C. Choinski,et al.  Generation of Digit Reversed Address Sequences for Fast Fourier Transforms , 1991, IEEE Trans. Computers.

[16]  Seung Ho Ok,et al.  A Digit Reversal Circuit for the Variable-Length Radix-4 FFT , 2007, Future Generation Communication and Networking (FGCN 2007).

[17]  Liang Yang,et al.  An efficient locally pipelined FFT processor , 2006, IEEE Trans. Circuits Syst. II Express Briefs.

[18]  M.N.S. Swamy,et al.  A fast FFT bit-reversal algorithm , 1994 .

[19]  M. Lopez-Vallejo,et al.  Implementing FFT-based digital channelized receivers on FPGA platforms , 2008, IEEE Transactions on Aerospace and Electronic Systems.

[20]  Larry Carter,et al.  Memory hierarchy considerations for fast transpose and bit-reversals , 1999, Proceedings Fifth International Symposium on High-Performance Computer Architecture.

[21]  Zhao Zhang,et al.  Cache-Optimal Methods for Bit-Reversals , 1999, ACM/IEEE SC 1999 Conference (SC'99).