Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology

The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.

[1]  R. Holzer.  A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  Kiyotaka Imai,et al.  A 0.10 /spl mu/m CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[3]  Stefan Kubicek,et al.  Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime , 2000 .

[4]  P. Larsson-Edefors,et al.  A gate leakage reduction strategy for future CMOS circuits , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[5]  Dan H. Wolaver,et al.  Phase-Locked Loop Circuit Design , 1991 .

[6]  N. Nguyen,et al.  A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[7]  Mohammed Ismail,et al.  Adaptive Miller capacitor multiplier for compact on-chip PLL filter , 2003 .

[8]  Xiaoyang Zeng,et al.  Compact current-mode loop filter for PLL applications , 2005 .

[9]  Zhongyuan Chang,et al.  A self-biased PLL with current-mode filter for clock generation , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  Chenming Hu,et al.  Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology] , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[11]  Zhiping Yu,et al.  Impact of gate direct tunneling current on circuit performance: a simulation study , 2001 .

[12]  C. Hu,et al.  BSIM4 gate leakage model including source-drain partition , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[13]  Jung-Suk Goo,et al.  Direct tunneling current model for circuit simulation , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).