Design Technique of an Integrated Gate Driver

Gate driver circuits are required in power switching converters to switch either their internal or external power MOSFETs. This paper presents a design procedure by optimizing the number of pre-driver inverters and their size ratios to minimize the signal delay of an integrated gate driver circuit for switching converters. The gate driver circuit was implemented in a 1.5µm CMOS process and tested successfully in a hysteretic synchronous buck switching converter. Delay due to anti-cross conduction circuitry is much smaller compared to the pre-driver delay, since minimum size devices are usually used in the shoot-through protection circuit. Pre-driver usually uses a string of inverter gates where the preceding gate is a couple of times narrower than the subsequent gate. The total number of inverters in the string and their size ratio are the critical design parameter to minimize the signal delay in the pre-driver. This paper presents a design technique of the pre-driver for minimum signal delay by selecting the right number of gates and their proper size ratios. This design technique can be applied to improve the control of the switching converter at high frequency operation (4-6).