Temperature analysis of underlap GAA-SNWTs for analog/RF applications

Abstract In the present work, a comprehensive study of temperature on gate-all-around silicon nanowire FETs (GAA-SNWTs) with source/drain underlap is performed to investigate the influence of Air as spacer dielectric, on analog/RF behavior of the device. The transconductance gm of the device enhances when the temperature is dropped down to 100 K. Thus, the analog/RF figure-of-merit (FOM) of the device enhances, rendering the device suitable for low temperature, low-power high-frequency operations. For targeting low power applications, FOMs are elicited at 10 μA/μm. It is perceived that the intrinsic gain of the device is marginally altered for distinct spacer dielectric (Si3N4 and air). Frequencies like cut-off frequency (fT) and maximum oscillation frequency (fMAX) of air spacer dielectric based underlap GAA-SNWTs are enhanced by 2.15 times and 1.73 times respectively when the operating temperature is dropped down to 100 K from 400 K. This results in higher percentage improvement in RF-FOM in terms of transconductance frequency product (TFP), gain-frequency product (GFP), and gain transconductance frequency product (GTFP).

[2]  Neha Gupta,et al.  Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability , 2016, Microelectron. Reliab..

[3]  Ashutosh Nandi,et al.  Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications , 2018, Materials Science in Semiconductor Processing.

[4]  R. Srinivasan,et al.  SET analysis of silicon nanotube FET , 2017 .

[5]  S. K. Mohapatra,et al.  Investigation on cylindrical gate all around (GAA) to nanowire MOSFET for circuit application , 2015 .

[6]  Rita Rooyackers,et al.  Multi-gate devices for the 32 nm technology node and beyond , 2008 .

[7]  S.C. Rustagi,et al.  CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach , 2007, IEEE Electron Device Letters.

[8]  V. L. Rideout,et al.  Very small MOSFET's for low-temperature operation , 1977, IEEE Transactions on Electron Devices.

[9]  Sudeb Dasgupta,et al.  Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths , 2014, IEEE Transactions on Electron Devices.

[10]  B. Yang,et al.  Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET , 2008, IEEE Electron Device Letters.

[11]  C. Hu,et al.  Air-Spacer MOSFET With Self-Aligned Contact for Future Dense Memories , 2009, IEEE Electron Device Letters.

[12]  A. Mercha,et al.  Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective , 2007, IEEE Transactions on Electron Devices.

[13]  V. Trivedi,et al.  Nanoscale FinFETs with gate-source/drain underlap , 2005, IEEE Transactions on Electron Devices.

[14]  Chenming Hu,et al.  Air spacer MOSFET technology for 20nm node and beyond , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[15]  Ashutosh Nandi,et al.  Effect of air spacer on analog performance of underlap tri-gate FinFET , 2017 .

[16]  Ashutosh Nandi,et al.  Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance , 2018, Cryogenics.

[17]  Sudeb Dasgupta,et al.  Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile , 2013, IEEE Transactions on Electron Devices.

[18]  G. A. Armstrong,et al.  Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications , 2007, IEEE Transactions on Electron Devices.

[19]  Sudeb Dasgupta,et al.  Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length , 2013, IEEE Transactions on Electron Devices.

[20]  Ru Huang,et al.  Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation , 2007, IEEE Transactions on Electron Devices.

[21]  Rishu Chaujar,et al.  Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET , 2015 .

[22]  N. Collaert,et al.  Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.

[23]  M. J. Kumar,et al.  Nanotube Junctionless FET: Proposal, Design, and Investigation , 2017, IEEE Transactions on Electron Devices.

[24]  Ru Huang,et al.  Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs , 2011, IEEE Transactions on Electron Devices.

[25]  C. Hu,et al.  Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications , 2017, IEEE Transactions on Electron Devices.

[26]  Yoon-Ha Jeong,et al.  Low-Temperature Performance of Nanoscale MOSFET for Deep-Space RF Applications , 2008, IEEE Electron Device Letters.

[27]  J.-P. Raskin,et al.  Optimizing FinFET geometry and parasitics for RF applications , 2008, 2008 IEEE International SOI Conference.

[28]  Chenming Hu,et al.  5nm-gate nanowire FinFET , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[29]  C. Hu,et al.  FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits , 2017, IEEE Electron Device Letters.

[30]  Seung-Hwan Kim,et al.  Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap , 2006, IEEE Transactions on Electron Devices.

[31]  L. Rubin.  Low Temperature Electronics: Physics, Devices, Circuits, and Applications , 2002 .

[32]  Ru Huang,et al.  Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors , 2015, IEEE Transactions on Electron Devices.

[33]  Ashutosh Nandi,et al.  Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM , 2018, Micro & Nano Letters.

[34]  M. Elbuluk,et al.  Power Electronic Components, Circuits and Systems for Deep Space Missions , 2005, 2005 IEEE 36th Power Electronics Specialists Conference.

[35]  Yee-Chia Yeo,et al.  Metal gate technology for nanoscale transistors—material selection and process integration issues , 2004 .