Inverter minimization in multi-level logic networks

n (his paper, we look al ~he probiem of inverter minimization in multi-level logic networks. The network is specified in lerrrrs of a set of base functions and the inversion operation. The library is specijied as a set of allowed permutations of phase assignments on each base function. Traditional approaches to lhis problem have been limited 10 greedy heuristics based on local information. Our approach takes a more global view and maps the problem of inverler minimization into a problem of removing a minimum of vertmes ji-om a graph, so as to make Ihe remaming graph 2colorable. This approach has the jk.zibility of capluring a variety of design -specific features ~hal are relevanl to lhe problem of inverter minimization. Al(hough, in general the problem is NPcomplete, we have developed several good heuristic and branch and bound search techniques.