A VLSI Architecture of JPEG 2000 Encoder

Abstract—This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimized Truncation (EBCOT). For DWT, a Spatial Combinative Lifting Algorithm (SCLA) based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations respectively compared with the conventional Lifting Based Implementation (LBI). For EBCOT, a Dynamic Memory Control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed-up the EBCOT Context Formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bit-stream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the Rate-Distortion (RD) truncation.