Sequential logic optimization by redundancy addition and removal
暂无分享,去创建一个
[1] Peter Muth,et al. A Nine-Valued Circuit Model for Test Generation , 1976, IEEE Transactions on Computers.
[2] Kwang-Ting Cheng. On removing redundancy in sequential circuits , 1991, 28th ACM/IEEE Design Automation Conference.
[3] M. Ray Mercer,et al. A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.
[4] Dhiraj K. Pradhan,et al. Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci , 1992, Proceedings International Test Conference 1992.
[5] Gary D. Hachtel,et al. BOLD: The Boulder Optimal Logic Design system , 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.
[6] Kwang-Ting Cheng,et al. Multi-level logic optimization by redundancy addition and removal , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[7] Robert K. Brayton,et al. Retiming and resynthesis: optimizing sequential networks with combinational techniques , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Fabio Somenzi,et al. Redundancy identification and removal based on implicit state enumeration , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[9] Masahiro Fujita,et al. Multi-level logic minimization across latch boundaries , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[10] Michael H. Schulz,et al. Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.