A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold

A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented. The ADC uses a technique to eliminate the front-end sample hold, thereby reducing power consumption. The technique allows for a power savings of 20% compared to a previous design. A method to improve the settling behavior of rapid power-on opamps is also presented. Measured results in a 1.8 V 0.18 CMOS process verify the removal of the front-end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With 50 MS/s, for the SNDR is 51.5 dB, and with 4.55 MS/s for the SNDR is 52.2 dB.

[1]  Christian Enz,et al.  CMOS low-power analog circuit design , 1996, Emerging Technologies: Designing Low Power Digital Systems.

[2]  Jan Craninckx,et al.  A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  J. Bjornsen,et al.  A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.

[4]  K. Martin,et al.  A 3.3 mW 12 MS/s 10b pipelined ADC in 90 nm digital CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[5]  Fan Ye,et al.  An Undersampling 10-bit 30.4-MSample/s Pipelined ADC , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[6]  Chi-Chang Lu,et al.  A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  D.A. Johns,et al.  A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[8]  J. Kornblum,et al.  A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter , 2006, IEEE Journal of Solid-State Circuits.

[9]  Dong-Young Chang,et al.  A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique , 2003 .

[10]  F. Kuttner,et al.  10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 /spl mu/m CMOS process , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[11]  Ho-Jin Park,et al.  A 1 mW 10-bit 500KSPS SAR A/D converter , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[12]  K. Bacrania,et al.  A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse , 2007, IEEE Journal of Solid-State Circuits.

[13]  I. Ahmed,et al.  A 50 MS/s (35 mW) to 1 kS/s (15 /spl mu/W) power scaleable 10b pipelined ADC with minimal bias current variation , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[14]  A.P. Chandrakasan,et al.  A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs , 2006, IEEE Journal of Solid-State Circuits.

[15]  Hae-Seung Lee,et al.  Comparator-based switched-capacitor circuits for scaled CMOS technologies , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[16]  I. Mehr,et al.  A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 1999, IEEE Journal of Solid-State Circuits.

[17]  Anders Vinje,et al.  A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[18]  Ying-Hsi Lin,et al.  A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[19]  Keng-Jan Hsiao,et al.  The design and analysis of a DLL-based frequency synthesizer for UWB application , 2006 .

[20]  Lei Xie,et al.  A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC , 2006, IEEE Custom Integrated Circuits Conference 2006.

[21]  G. Nicollini,et al.  A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[22]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[23]  Paul R. Gray,et al.  A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[24]  Mohammed Ismail,et al.  Reconfigurable ADCs enable smart radios for 4G wireless connectivity , 2006 .

[25]  Shoji Kawahito,et al.  A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture , 2003, IEEE J. Solid State Circuits.

[26]  William J. Dally,et al.  Digital systems engineering , 1998 .

[27]  M. Anderson,et al.  A reconfigurable pipelined ADC in 0.18 /spl mu/m CMOS , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[28]  P. C. Maulik,et al.  A DLL-Based Programmable Clock Multiplier in 0.18-$\mu$ m CMOS With ${-}$70 dBc Reference Spur , 2007, IEEE Journal of Solid-State Circuits.

[29]  Yun Chiu,et al.  A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[30]  E. Sanchez-Sinencio,et al.  A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver , 2006, IEEE Journal of Solid-State Circuits.

[31]  O. Moldsvor,et al.  A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13/spl mu/m digital CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[32]  Kush Gulati,et al.  A low-power reconfigurable analog-to-digital converter , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[33]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[34]  R. Castello,et al.  A 6-10 bits Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[35]  J. Arias,et al.  Low-power pipeline ADC for wireless LANs , 2004, IEEE Journal of Solid-State Circuits.

[36]  Bjørnar Hernes,et al.  A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS , 2005 .

[37]  A.P. Chandrakasan,et al.  An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes , 2007, IEEE Journal of Solid-State Circuits.