Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and other devices. In this study, HAR TSVs with a diameter of 11 μm and an aspect ratio of 10:1 are successfully fabricated in a low-cost process flow. Conformal polyimide (PI) liners are deposited using a vacuum-assisted spin coating technique, and the effects of spin coating time and speed on the deposition results are discussed. Then, continuous Cu seed layers are fabricated by sequential sputtering and ultrasound-assisted electroless plating. Additionally, void-free and seamless Cu conductors are formed by electroplating. Moreover, a semi-additive method is used to fabricate the redistribution layers (RDLs) on the insulating layers of photosensitive PI (PSPI). Notably, a plasma bombardment process is introduced to remove residual PSPI in the contact windows between RDLs and central pillars. Results show that the resistance of a single TSV from a daisy chain of 144 TSVs with density of 2000/mm2 is about 28 mΩ. Additionally, the S-parameters of a single TSV are obtained using L-2L de-embedding technology, and the experimental and simulated results agree well. The proposed low-cost fabrication technologies and the related electrical characterization of PI-TSVs are significant for the application of HAR TSVs in modern heterogeneous integration systems.

[1]  Zhiming Chen,et al.  Ultra-Deep Annular Cu Through-Silicon-Vias Fabricated Using Single-Sided Process , 2022, IEEE Electron Device Letters.

[2]  Zhiming Chen,et al.  Enabling Continuous Cu Seed Layer for Deep Through-Silicon-Vias With High Aspect Ratio by Sequential Sputtering and Electroless Plating , 2021, IEEE Electron Device Letters.

[3]  H. Wong.  On the CMOS Device Downsizing, More Moore, More than Moore, and More-than-Moore for More Moore , 2021, 2021 IEEE 32nd International Conference on Microelectronics (MIEL).

[4]  Xue Luo,et al.  Crack-Free Fabrication and Electrical Characterization of Coaxial Ultra-Low-Resistivity-Silicon Through-Silicon-Vias , 2020, IEEE Transactions on Semiconductor Manufacturing.

[5]  Liang He,et al.  A Review: Preparation, Performance, and Applications of Silicon Oxynitride Film , 2019, Micromachines.

[6]  Zheyao Wang,et al.  Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications , 2019, Microelectronic Engineering.

[7]  Tetsu Tanaka,et al.  Development of Eccentric Spin Coating of Polymer Liner for Low-Temperature TSV Technology With Ultra-Fine Diameter , 2019, IEEE Electron Device Letters.

[8]  Zhiming Chen,et al.  Impact of polyimide liner on high-aspect-ratio through-silicon-vias (TSVs): electrical characteristics and copper protrusion , 2017 .

[9]  Wen-Wei Shen,et al.  Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV) , 2017, Nanoscale Research Letters.

[10]  B. Liu,et al.  Low capacitance and highly reliable blind through-silicon-vias (TSVs) with vacuum-assisted spin coating of polyimide dielectric liners , 2016 .

[11]  K. Moon,et al.  Formation of Polymer Insulation Layer (Liner) on Through Silicon Vias (TSV) with High Aspect Ratio over 5:1 by Direct Spin Coating , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[12]  M. Koyanagi,et al.  Capacitance characteristics of low-k low-cost CVD grown polyimide liner for high-density Cu through-Si-via in three-dimensional LSI , 2016 .

[13]  M. Koyanagi,et al.  Study of Vacuum-Assisted Spin Coating of Polymer Liner for High-Aspect-Ratio Through-Silicon-Via Applications , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[14]  Zheyao Wang,et al.  Low-Capacitance Through-Silicon-Vias With Combined Air/SiO2 Liners , 2016, IEEE Transactions on Electron Devices.

[15]  Paragkumar Thadesar,et al.  Fabrication and Characterization of Polymer-Enhanced TSVs, Inductors, and Antennas for Mixed-Signal Silicon Interposer Platforms , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[16]  Mitsu Koyanagi,et al.  Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications , 2015, 2015 International 3D Systems Integration Conference (3DIC).

[17]  Zheyao Wang.  3-D Integration and Through-Silicon Vias in MEMS and Microsensors , 2015, Journal of Microelectromechanical Systems.

[18]  M. Koyanagi,et al.  Improved C-V, I–V characteristics for co-polymerized organic liner in the Through-Silicon-Via for high frequency applications by post heat treatment , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[19]  Wenqi Zhang,et al.  Fabrication of dielectric insulation layers in TSV by different processes , 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

[20]  K. Chui,et al.  Through silicon via (TSV) scallop smoothening technique , 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

[21]  M. Koyanagi,et al.  Highly beneficial organic liner with extremely low Thermal stress for fine Cu-TSV in 3D-integration , 2014, 2014 IEEE International Electron Devices Meeting.

[22]  Yangyang Yan,et al.  Analytical solution on interfacial reliability of 3-D through-silicon-via (TSV) containing dielectric liner , 2014, Microelectron. Reliab..

[23]  M. Koyanagi,et al.  Mechanical Characteristics of Thin Die/Wafers in Three-Dimensional Large-Scale Integrated Systems , 2014, IEEE Transactions on Semiconductor Manufacturing.

[24]  Fumihiro Inoue,et al.  Highly conformal and adhesive electroless barrier and Cu seed formation using nanoparticle catalyst for realizing a high aspect ratio cu-filled TSV , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

[25]  M. Koyanagi,et al.  Low-Temperature and High-Step-Coverage Polyimide TSV Liner Formation by Vapor Deposition Polymerization , 2013 .

[26]  Zheng Xu,et al.  TSV density impact on 3D power delivery with high aspect ratio TSVs , 2013, ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference.

[27]  M. F. Chen,et al.  TSV RF de-embedding method and modeling for 3DIC , 2012, 2012 SEMI Advanced Semiconductor Manufacturing Conference.

[28]  Shekhar Y. Borkar,et al.  Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration , 2011, IET Comput. Digit. Tech..

[29]  T. Kurihara,et al.  Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring , 2008, 2008 58th Electronic Components and Technology Conference.

[30]  Payman Zarkesh-Ha,et al.  Global interconnect design in a three-dimensional system-on-a-chip , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[31]  James D. Meindl,et al.  Interconnect Opportunities for Gigascale Integration , 2002, IEEE Micro.

[32]  P.C.H. Chan,et al.  Fabrication of gate-all-around transistors using metal induced lateral crystallization , 2001, IEEE Electron Device Letters.

[33]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .