Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit

This paper presents thermo-mechanical investigation results of a reconfigurable wafer-scale integrated circuit, the WaferIC™, dedicated to electronic systems prototyping. The proposed approach carefully selects materials combined with an active cooling mechanism to avoid critical localized thermal peaks and associated large thermal stresses. The performance of the approach was evaluated and tested using finite element methods and steady state thermo-mechanical results are provided. During the development of the WaferIC, the thermo-mechanical design aspects were proven crucial to its reliable operation. Large and possibly excessive values of stress can be induced on the WaferIC by a variety of operations and processing steps during fabrication, including attachment and encapsulation, if not properly designed.

[1]  C. Perret,et al.  Analytic modeling, optimization, and realization of cooling devices in silicon technology , 2000 .

[2]  Y. Blaquiere,et al.  An interconnection network for a novel reconfigurable circuit board , 2008, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference.

[3]  B. Dang,et al.  Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics , 2005, IEEE Transactions on Advanced Packaging.

[4]  Y. Blaquiere,et al.  An active reconfigurable circuit board , 2008, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference.

[5]  Y. Blaquiere,et al.  Steady state thermal analysis of a reconfigurable wafer-scale circuit board , 2008, 2008 Canadian Conference on Electrical and Computer Engineering.

[6]  D. J. Walkey,et al.  A simulation study of IC layout effects on thermal management of die attached GaAs ICs , 2000 .