HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation
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[1] K. Langendoen,et al. Integrating polling, interrupts, and thread management , 1996, Proceedings of 6th Symposium on the Frontiers of Massively Parallel Computation (Frontiers '96).
[2] Brice Goglin,et al. Finding a tradeoff between host interrupt load and MPI latency over Ethernet , 2009, 2009 IEEE International Conference on Cluster Computing and Workshops.
[3] Michael A. Hicks,et al. Towards scalable I/O on a many-core architecture , 2010, 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.
[4] C. R. Jesshope,et al. Dynamic scheduling in RISC architectures , 1996 .
[5] Francesco Regazzoni,et al. Hardware Scheduling Support in SMP Architectures , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[6] Wolfgang Schröder-Preikschat,et al. Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system , 2009, CASES '09.
[7] Corporate Inmos Limited. Transputer Reference Manual , 1988 .
[8] Chris R. Jesshope,et al. Implementation and evaluation of a microthread architecture , 2009, J. Syst. Archit..
[9] Jari Nurmi,et al. High-performance NoC Interface with interrupt batching for Micronmesh MPSoC prototype platform on FPGA , 2010, NORCHIP 2010.
[10] Rainer Leupers,et al. Task management in MPSoCs: An ASIP approach , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[11] Kees van Berkel,et al. Multi-core for mobile phones , 2009, DATE.