A High-Speed Sample and Hold Circuit for Pipelined A/D Converter

In this paper,a sample and hold circuit for a 10bit 80MS/s pipelined A/D converter has been designed,which is implemented in a TSMC 0.25μm CMOS process.The S/H circuit is realized in switched-capacitor topology.Using switch gate voltage bootstrapping for constant Vgs and bottom plate sampling techniques,nonlinear distortion is reduced significantly.The A/D converter based on this S/H circuit achieves a SFDR of 84.9dB at 80MHz sampling rate.