An Ultra-Compact Hardware Implementation of SMS4

SMS4 is widely used in the Chinese National Standard for Wireless LAN WAPI (Wired Authentication and Privacy Infrastructure), and in WLAN WAPI, low-cost and efficient cryptography algorithm implementation is necessary and challenging. This paper proposes an ultra-compact IP core architecture, where the input data is processed in bytes. The proposed architecture further reduces its hardware consumption by reutilizing its resources and rescheduling its procedures. When implemented on the Virtex-4 FPGA platform, the hardware resource consumption of the architecture falls to 30% of the latest work, while the ratio of the throughput to the area remains almost unchanged. It is also implemented on ASIC platform and the synthesis result shows the SMS4 IP core proposed in this paper is quite diminutive and is very suitable for embedded systems.

[1]  Kris Gaj,et al.  Very Compact FPGA Implementation of the AES Algorithm , 2003, CHES.

[2]  Haibin Shen,et al.  Implementation of SMS4 Block Cipher on FPGA , 2006, 2006 First International Conference on Communications and Networking in China.

[3]  Erhong Lu,et al.  FPGA Implementation of the SMS4 Block Cipher in the Chinese WAPI Standard , 2008, 2008 International Conference on Embedded Software and Systems Symposia.

[4]  Wu Meng.  Pipelined High-Speed Implementation of SMS4 , 2007 .

[5]  Cheng Wang,et al.  An ultra compact block cipher for serialized architecture implementations , 2009, 2009 Canadian Conference on Electrical and Computer Engineering.

[6]  Christof Paar,et al.  Pushing the Limits: A Very Compact and a Threshold Implementation of AES , 2011, EUROCRYPT.

[7]  Tim Good,et al.  Very small FPGA application-specific instruction processor for AES , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Wenrui Ding,et al.  Fast Implementation of SMS4 Cryptographic Algorithms on Smart Card , 2008, 2008 International Conference on Intelligent Information Hiding and Multimedia Signal Processing.

[9]  Jean-Didier Legat,et al.  Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[10]  Han Bixia.  Research of SMS4's Implementation in Hardware Based on Embedded System , 2008 .

[11]  Li Shuguo,et al.  High Performance FPGA Implementation for SMS4 , 2011 .

[12]  S. Choomchuay,et al.  A 32 bits architecture for an AES system , 2004, IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004..

[13]  Liu Hui-zhong.  High-speed implementation of SMS4 based on FPGA , 2010 .

[14]  Zongbin Liu,et al.  HPAZ: A high-throughput pipeline architecture of ZUC in hardware , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).