SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis

IDDQ testing uses an important property of CMOS ICs that in the steady state, the current consumption is very small. Therefore, a higher steady state current is an indicator of a probable process defect. Published literature gives ample evidence that elevation in the steady state current could be caused due to a variety of reasons besides process defects. As technology moves into deep sub-micron region, the increase in various transistor leakage currents have the potential of reducing theIDDQ effectiveness. In this article, we propose the separation of VDD and VSS supplies for signal and bias paths so that various leakage current components are measured or computed. The methodology provides means for unambiguousIDDQ testing, better defect diagnosis, and can be used for deep sub-micronIDDQ testing.