A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique

This paper proposes a continuous-rate referenceless clock and data recovery (CDR) circuit operating in the half-rate clocking mode with a jitter-tolerant frequency acquisition technique. The proposed coarse frequency detector reduces frequency error below 40,000 ppm without any sub-harmonic lock even when the input jitter presents up to 0.6 UIpp. The deadzone-compensated frequency detector further reduces the residual frequency error below 1,000 ppm for the following PLL's reliable operation. The CDR fabricated in a 28-nm CMOS process shows a wide capture range of 4.0 Gb/s to 10.0 Gb/s with a bit error rate (BER) under 10−12.