A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches

Circuit techniques for enabling a sub-0.9 V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes Read Word-line (RWL) preferential boosting to increase read margin and improve data retention time. Read speed is enhanced with a hybrid current/voltage sense amplifier that allows the Read Bit-line (RBL) to remain close to VDD. A regulated bit-line write scheme for driving the Write Bit-line (WBL) is equipped with a steady-state storage node voltage monitor to overcome the data `1' write disturbance problem of the PMOS gain cell without introducing another boosted supply for the Write Word-line (WWL) over-drive. An adaptive and die-to-die adjustable read reference bias generator is proposed to cope with PVT variations. Monte Carlo simulations compare the 6-sigma read and write performance of proposed eDRAM against conventional designs. Measurement results from a 64 kb eDRAM test chip implemented in a 65 nm low-leakage CMOS process show a 1.25 ms data retention time with a 2 ns random cycle time at 0.9 V, 85°C, and a 91.3 μW per Mb static power dissipation at 1.0 V, 85°C.

[1]  W. Luk,et al.  A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[2]  Richard E. Matick,et al.  A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier , 2008, IEEE Journal of Solid-State Circuits.

[3]  Sani R. Nassif,et al.  The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  C.H. Kim,et al.  PVT-aware leakage reduction for on-die caches with improved read stability , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[5]  Sreedhar Natarajan,et al.  A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Jae-Yoon Sim,et al.  A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor , 2003 .

[7]  Yibin Ye,et al.  2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology , 2009, IEEE Journal of Solid-State Circuits.

[8]  Paolo A. Aseron,et al.  2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  N. Vallepalli,et al.  SRAM design on 65nm CMOS technology with integrated leakage reduction scheme , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[10]  Jonathan Chang,et al.  A 45nm 24MB on-die L3 cache for the 8-core multi-threaded Xeon® Processor , 2009, 2009 Symposium on VLSI Circuits.

[11]  Evert Seevinck,et al.  Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's , 1991 .

[12]  Chris H. Kim,et al.  A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias , 2009, 2009 Symposium on VLSI Circuits.

[13]  Erik Nelson,et al.  A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS , 2009, IEEE Journal of Solid-State Circuits.

[14]  Richard E. Matick,et al.  Logic-based eDRAM: Origins and rationale for use , 2005, IBM J. Res. Dev..

[15]  Balaram Sinharoy,et al.  POWER7: IBM's next generation server processor , 2010, 2009 IEEE Hot Chips 21 Symposium (HCS).