The Reconfigurable Instruction Cell Array

This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.

[1]  Pascal Benoit,et al.  Automatic task scheduling/loop unrolling using dedicated RTR controllers in coarse grain reconfigurable architectures , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[2]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[3]  Rupert Baines,et al.  A total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers , 2003, IEEE Commun. Mag..

[4]  Gerard J. M. Smit,et al.  Montium - Balancing between Energy-Efficiency, Flexibility and Performance , 2003, Engineering of Reconfigurable Systems and Algorithms.

[5]  Gerald Estrin,et al.  Reconfigurable Computer Origins: The UCLA Fixed-Plus-Variable (F+V) Structure Computer , 2002, IEEE Ann. Hist. Comput..

[6]  Carl Ebeling,et al.  Implementing an OFDM receiver on the RaPiD reconfigurable architecture , 2003, IEEE Transactions on Computers.

[7]  Paolo Ienne,et al.  A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units , 2002, 15th International Symposium on System Synthesis, 2002..

[8]  Tughrul Arslan,et al.  Efficient implementations of mobile video computations on domain-specific reconfigurable arrays , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[9]  Tughrul Arslan,et al.  Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems , 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

[10]  Tughrul Arslan,et al.  Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems , 2007 .

[11]  Tughrul Arslan,et al.  System-level Scheduling on Instruction Cell Based Reconfigurable Systems , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[12]  Tim Güneysu,et al.  New Protection Mechanisms for Intellectual Property in Reconfigurable Logic , 2007 .

[13]  Stephen D. Brown,et al.  Flexibility of interconnection structures for field-programmable gate arrays , 1991 .

[14]  Christos-Savvas Bouganis,et al.  Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs , 2007 .

[15]  Gerald Estrin,et al.  Organization of Computer Systems-the Fixed Plus Variable Structure Computer , 1899 .

[16]  John Wawrzynek,et al.  Augmenting a microprocessor with reconfigurable hardware , 2000 .

[17]  Tughrul Arslan,et al.  Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[18]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[19]  Rudy Lauwereins,et al.  Low Power Coarse-Grained Reconfigurable Instruction Set Processor , 2003, FPL.

[20]  Junqiang Sun,et al.  Tms320c6000 cpu and instruction set reference guide , 2000 .

[21]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[22]  P. Groves,et al.  A 600 MHz VLIW DSP , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[23]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[24]  George Varghese,et al.  Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System , 2001, J. VLSI Signal Process..

[25]  David Wentzlaff Architectural implications of bit-level computation in communication applications , 2002 .

[26]  D. Bhatia,et al.  Reconfigurable computing , 1997, Proceedings Tenth International Conference on VLSI Design.