Yield Improvement, Fault-Tolerance to the Rescue?

With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.

[1]  A. Singh,et al.  Fault-tolerant systems , 1990, Computer.

[2]  Michael S. Hsiao,et al.  Bilateral Testing of Nano-scale Fault-tolerant Circuits , 2006, DFT.

[3]  Yvon Savaria,et al.  Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model , 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[4]  Charles E. Stroud,et al.  Design for testability and test generation for static redundancy system level fault-tolerant circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.