In order to narrow the speed and density gap between FPGAs and MPGAs we propose the development of "families" of FPGAs. Each FPGA family is targeted at a single maximum logic capacity, and consists of several "siblings", or FPGAs of different yet complementary architectures. Any given application circuit is implemented in the sibling with the most appropriate architecture. With properly chosen siblings, one can develop a family of FPGAs which will have better speed and density than any single FPGA. We apply this concept to create two different FPGA families, one composed of architectures with different types of hard-wired logic blocks and the other created from architectures with different types of heterogeneous logic blocks. We found that a family composed of eight chips with different hard-wired logic block architectures simultaneously improves density by 12 to 14% and speed by 18 to 20% over the best single hard-wired FPGA.
[1]
Kevin Charles Kenton Chung.
Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections
,
1994
.
[2]
Jonathan Rose,et al.
The effect of logic block architecture on FPGA performance
,
1992
.
[3]
Jonathan Rose,et al.
Advantages of Heterogeneous Logic Block Architectures for
,
1993
.
[4]
Philip J. Fleming,et al.
How not to lie with statistics: the correct way to summarize benchmark results
,
1986,
CACM.
[5]
Jonathan Rose,et al.
Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency
,
1990
.
[6]
A. El Gamal,et al.
Architecture of field-programmable gate arrays
,
1993,
Proc. IEEE.