A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS

A U-band phase-locked loop (PLL) with implicit distributed resonators in the voltage-controlled oscillator (VCO) and injection-locked frequency divider (ILFD) using 40 nm CMOS is investigated in this brief. While LC-based, transformer-based, and distributed resonators are typically adopted for mm-wave and sub-terahertz applications, implicit distributed resonators are proposed to enhance the oscillation frequency of the VCO and expand the locking range of the ILFD. The operating principles and the characteristics of the proposed implicit distributed resonators are discussed for intuitive insight. The presented PLL occupies 0.53 mm2 core area and has 81.8 mW power consumption. The PLL achieves a measured frequency range of 8.15 GHz (16%) from 46.75 GHz to 54.9 GHz. The measured phase noise is −91.8 dBc/Hz at 1 MHz offset frequency from a carrier of 46.75 GHz. The proposed U-band PLL can provide a clear and stable local oscillation signal for the transceivers operating at mm-wave and sub-terahertz (sub-THz) frequency band.

[1]  Howard C. Luong,et al.  Analysis and Design of Wide-Band Millimeter-Wave Transformer-Based VCO and ILFDs , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Kai Kang,et al.  Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators , 2018, IEEE Journal of Solid-State Circuits.

[3]  Ali M. Niknejad,et al.  A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[4]  Howard C. Luong,et al.  Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS , 2015, IEEE Transactions on Microwave Theory and Techniques.

[5]  Yanping Ding,et al.  A 50-GHz Phase-Locked Loop in 0.13-$\mu$ m CMOS , 2007, IEEE Journal of Solid-State Circuits.

[6]  Payam Heydari,et al.  A CMOS V-Band PLL With a Harmonic Positive Feedback VCO Leveraging Operation in Triode Region for Phase-Noise Improvement , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Bo-Yu Lin,et al.  Analysis and Design of D-Band Injection-Locked Frequency Dividers , 2011, IEEE Journal of Solid-State Circuits.

[8]  Kenichi Okada,et al.  A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad , 2016, IEEE Journal of Solid-State Circuits.

[9]  Jongwon Yun,et al.  Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology , 2016, IEEE Transactions on Microwave Theory and Techniques.

[10]  Shahriar Mirabbasi,et al.  On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise , 2016, IEEE Journal of Solid-State Circuits.

[11]  Minoru Fujishima,et al.  9.5 An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

[12]  Kevin Chen,et al.  A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider , 2016, 2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

[13]  Chung-Yu Wu,et al.  Design and Analysis of a Millimeter-Wave Direct Injection-Locked Frequency Divider With Large Frequency Locking Range , 2007, IEEE Transactions on Microwave Theory and Techniques.

[14]  B. Chi,et al.  A 47.6–71.0-GHz 65-nm CMOS VCO Based on Magnetically Coupled $\pi $-Type LC Network , 2015, IEEE Transactions on Microwave Theory and Techniques.

[15]  Baoyong Chi,et al.  A Fully Integrated 150-GHz Transceiver Front-End in 65-nm CMOS , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.