Complete Test Sets for Logic Functions

The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid.

[1]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[2]  Sudhakar M. Reddy,et al.  A Design Procedure for Fault-Locatable Switching Circuits , 1972, IEEE Transactions on Computers.

[3]  Rodolfo Betancourt Derivation of Minimum Test Sets for Unate Logical Circuits , 1971, IEEE Transactions on Computers.

[4]  Sheldon B. Akers Universal Test Sets for Logic Networks , 1973, IEEE Transactions on Computers.

[5]  Se June Hong,et al.  Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks , 1971, IEEE Transactions on Computers.

[6]  Arthur D. Friedman Fault Detection in Redundant Circuits , 1967, IEEE Trans. Electron. Comput..

[7]  A. Mukhopadhyay Unate Cellular Logic , 1969, IEEE Transactions on Computers.