Off chip monitors and built in current sensors for analogue and mixed signal testing

The aim of this paper is to be part a general survey regarding test methods for analogue and mixed circuits, using a stimulus on the signal or power supply inputs. The data is extracted from the power supply current I/sub DD/. It is based on the fruitful measurement of the I/sub DDQ/, the DC power supply current, as well as the measurement of the I/sub DDT/, the transient power supply current. This paper presents the state of the art of the existing current monitors sorted according to their sensitive element.

[1]  Joan Figueras,et al.  Proportional BIC sensor for current testing , 1992, J. Electron. Test..

[2]  Sudhakar Reddy,et al.  Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops , 1986, IEEE Design & Test of Computers.

[3]  Kenneth M. Wallquist Achieving I/sub DDQ/I/sub SSQ/ production testing with QuiC- , 1995, IEEE Design & Test of Computers.

[4]  S.R. Makar,et al.  Some faults need an I/sub ddq/ test , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.

[5]  A. D. Singh,et al.  A differential built-in current sensor design for high-speed IDDQ testing , 1997 .

[6]  Yann Deval,et al.  Using IDD to analyze analog faults and development of a sensor , 1996, Advanced Lithography.

[7]  R. Rajsuman,et al.  Iddq testing for CMOS VLSI , 1994, Proceedings of the IEEE.

[8]  J.P.M. van Lammeren I/sub CCQ/: a test method for analogue VLSI based on current monitoring , 1997 .

[9]  Edward J. McCluskey,et al.  Some faults need an Iddq test , 1996 .

[10]  M. Hashizume,et al.  A current sensing circuit for feedback bridging faults , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[11]  Ching-Wen Hsue,et al.  Built-In Current Sensor for IDDQ Test in CMOS , 1993 .

[12]  Keith Baker,et al.  Development of a class 1 QTAG monitor , 1994, Proceedings., International Test Conference.

[13]  Yoshihiro Hashimoto,et al.  High-speed I/sub DDQ/ measurement circuit , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[14]  Jien-Chung Lo,et al.  A 2-ns detecting time, 2- mu m CMOS built-in current sensing circuit , 1993 .

[15]  M. Ray Mercer,et al.  Iddq testing for high performance CMOS-the next ten years , 1996, Proceedings ED&TC European Design and Test Conference.

[16]  Y. Deval,et al.  On-line CMOS BICS: an experimental study , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[17]  Melvin A. Breuer,et al.  A universal test sequence for CMOS scan registers , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[18]  Viera Stopjaková,et al.  CCII+ current conveyor based BIC monitor for I/sub DDQ/ testing of complex CMOS circuits , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[19]  Kenneth M. Wallquist,et al.  A general purpose I/sub DDQ/ measurement circuit , 1993, Proceedings of IEEE International Test Conference - (ITC).

[20]  Ching-Wen Hsue,et al.  Built-in current sensor for I/sub DDQ/ test in CMOS , 1993, Proceedings of IEEE International Test Conference - (ITC).

[21]  Jos van Sas,et al.  An off-chip IDDq current measurement unit for telecommunication ASICs , 1994, Proceedings., International Test Conference.

[22]  S.M. Menon,et al.  Estimation of partition size for I/sub DDQ/ testing using built-in current sensing , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[23]  H. Yamazaki,et al.  IDDQ testability of flip-flop structures , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.

[24]  Wojciech Maly,et al.  Built-in current testing-feasibility study , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[25]  M. Sachdev,et al.  I/sub DDQ/ testable dynamic PLAs , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[26]  Jan B. Wilstrup,et al.  A general purpose ATE based I/sub DDQ/ measurement circuit , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[27]  Manoj Sachdev Reducing the CMOS RAM test complexity withIDDQ and voltage testing , 1995, J. Electron. Test..